FIR implementation(1)

Among the most fundamental and widely implemented DSP components is the Finite Impulse Response (FIR) filter. Here we want to show the implementation of the FIR filter using HLS.

Project goal: FIR implementation using Vivado HLS
In below steps you see how we got it done with the aid of Vivado HLS:
⦁ First step: We designed an FIR filter in Matlab with fdatool and exported coefficients as 16-bit integers. It is a low pass filter with cut-off frequency of 5MHz and attenuation of around 60dB in Stop-band.
⦁ We developed the FIR filter in C++, wrote result into a file as a simulation reference for use in HLS
⦁ The full flow consists of C simulation, Synthesis and RTL Co-simulation in Vivado HLS. Then the last step is to export the IP. Besides, Additionally, we used some techniques to improve the performance of the core.
⦁ As the final step, we used the generated IP in a project in Vivado and simulated it.
⦁ Input signal to test bench has these specification: Sinewave in pass-band region of FIR filter, it is 1MHz, another sinewave as the noise, with the frequency of 6MHz was added to the main signal.

⦁ Fourier Analysis of input:

Below picture is the input and output of final design simulation with XSim:

Below picture is the Fourier representation of final output. It shows two frequency bins, one for the main harmonic and the other one is what we had added to the input as unwanted signal which our FIR filter has attenuated it.

By reporting these two curser points to the workspace and calculating dB differences we reached to the attenuation of about 56 dB

Summary:

We showed how Vitis HLS is capable of converting a high level algorithm into an IP core that can be deployed on FPGA. This link is the project link in github.